Back

Building a HIL Rig for MentorPi-A1's Battery Pack, and What It Caught Before We Ever Charged It

The real cell arrived three weeks late. By the time it showed up, the simulated one had already failed on us four times — for free.

Electronics Lab Bench With Battery Testing Setup

The real cell arrived three weeks late. By the time it showed up, the simulated one had already failed on us four times — for free.


Here's the question I actually had, unfiltered, the week I found out the replacement pack was four weeks out instead of one: why not just wait? The BMS firmware was already written. The spec was reviewed. Building a simulated four-cell pack in Simulink felt like effort I'd throw away the moment a real cell showed up on the bench — busywork dressed up as progress against a deadline that had just gotten a lot less urgent.

Trying the Thought Experiment: What If We Just Waited for the Real Pack?

The way I actually worked through this wasn't by reading a Model-Based Design pitch — it was by imagining the first week the real pack sat on the bench, running the same tests I'd eventually run in simulation, except for real. Command a hard short on one channel and see what happens. Ramp the pack temperature past the cutoff and see if the firmware actually cuts. Unbalance one cell by 400mV and watch whether the balancer notices.

Imagined that way, waiting stopped sounding like the safe option. Overcurrent, cell imbalance, and thermal runaway don't announce themselves gently on a real lithium cell, and "let's just try it and see" is exactly the wrong instinct for code whose entire job is catching the moment things go wrong. If the BMS logic had a bug — and it always has a bug the first time it meets real hardware — the real pack would be the one to find it, and there was no guarantee that discovery would be cheap.

opengen-a9ff1e02-a29f-4c8e-a0d2-adaa6aec9e5d

What the HIL Rig Is Actually For

This is the point where building a simulated pack stopped looking like busywork and started looking like the obvious move. I modeled the pack as four series cells with individual state-of-charge and internal-resistance dynamics, wrapped the whole thing in the same balancing and protection logic that was going to run on the real board, and put it on our small real-time target so the BMS firmware couldn't tell the difference between the simulated pack and a physical one sitting on the bench. Then I started doing the things I'd never do to a real cell on day one: commanding a hard short on one channel, ramping the pack temperature past the cutoff in software, unbalancing one cell by 400mV — except now with nothing to lose.

It caught three real bugs before the physical pack ever arrived. The one I still think about is the thermal cutoff — the threshold was set correctly in the spec, correctly in the code, and wrong in the units. Someone (me, if I'm honest about the git blame) had wired the comparison against a raw ADC count instead of the converted temperature, so the cutoff was firing about 40°C later than it should have. In simulation, that's a graph that looks wrong. On a real pack, that's the difference between a beeping fault light and a very bad afternoon.

By the time the real cells showed up, the firmware had already been through four failures and four fixes that cost us nothing but simulation time. Bring-up on the actual hardware took an afternoon instead of a week, and the only surprise left was a connector that didn't fit — which, to be fair, no model could have told me.

The rig isn't going anywhere. It's still sitting on the bench, still wired into the RRC Lite board, and it's going to be the first thing every future pack revision has to survive before it gets anywhere near a real cell.